1. Field of the Invention
The present invention relates to a device for testing a phase-locked loop (PLL) and a method thereof.
2. Description of the Related Art
The PLL is indispensable in complex high-frequency synchronous systems because of the difficulty in the distribution of reliable low-skew high-frequency clock signal throughout the various package technologies of a complex system.
The benefits of utilizing PLL-based clock distribution for high-frequency synchronous systems is particularly clear in the design of a complex high-performance machine such as a server. A high-frequency synchronous system employs a variety of packaging technologies, including single-chip modules (SCMs), multichip modules (MCMs), cards, and boards. The distribution of a reliable low-skew high-frequency clock signal throughout these various package technologies is, to say the least, difficult. The PLL-based design facilitates distribution of a relatively low-frequency reference oscillator to each of the components. Each component contains a PLL, which then multiplies that frequency to a higher frequency that it requires while maintaining proper phase alignment for a synchronous design. The ability of the PLL to multiply the reference oscillator frequency is critical, Far since the synchronous system may have a number of components running at different frequencies (G. A. Van Huben, T. G. McNamara and T. E. Gilbert, xe2x80x9cPLL modeling and verification in a cycle-simulation environment,xe2x80x9d IBM Journal of Research and Development, Vol. 43, No. 5/6, 1999).
Another advantage of the PLL-based design concept is that it permits the use of programmable ratios among a collection of system components. Assume a subsystem is supposed to run at a specified number of times slower than another, say a processor. If the chips of the subsystem were actually to run faster or slower than the specified frequency, the multiplier bits of the subsystem PLL could be reprogrammed with a new xe2x80x9cgear ratio.xe2x80x9d As long as the on-chip clock logic is capable of supporting a different frequency, the system ratios can be reprogrammed without the risk of introducing frequency-sensitive anomalies into the rest of the system. It is critical to keep the clock skew between the various components of a synchronous system very low. The PLL for each component phase-aligns its on-chip clock distribution delay. PLLs are also used in frequency synthesizers, analog and digital modulators and demodulators.
A PLL is described as a system that uses feedback to maintain an output signal in a specific phase relationship with a reference signal in the following reference.
Steven L. Maddy, xe2x80x9cPhase-Locked Loop,xe2x80x9d Chapter 70 of The Electrical Engineering Handbook, editor-in-chief: Richard C. Dorf, IEEE Press, CRC Press, pp. 1567-1575, 1993.
FIG. 1 shows a configuration of such a PLL. As explained above, the frequency of the output signal of the PLL is a multiple of the frequency of its input signal.
Phase comparator 11 produces an output combination that is dependent on the phase difference of the two input signals CK and FB, where CK is the reference signal input. It is a state-machine triggered by the rising edges of the input signals CK and FB and produces the output signals UP and DN. The state diagram is as shown in FIG. 2. As illustrated in FIG. 2, the state-machine has a discharge state 21, a hold state 22 and a charge state 23. Lock detector 16 produces a single observable output signal L that is dependent on the phase difference of the two input signals.
Charge pump 12 consists of two CMOS (complementary metal-oxide semiconductor) switches, as illustrated in FIG. 3, controlled by the states of the phase comparator 11. FIG. 4 shows how the charge pump 12 functions. When the signal UP is low (logic 0), the switch 31 connects the node of output signal Vout to VDD, and when the signal DN is low, the switch 32 connects the node to VSS. When both signals UP and DN are high (logic 1), the node is isolated from VDD and VSS and voltage Vop on a capacitor of loop filter (LPF) 13 appears as Vout.
The loop filter 13 is a low-pass filter and is used to control the PLL dynamics and therefore the performance of the PLL. Voltage-controlled oscillator (VCO) 14 is a circuit that produces an AC (alternating current) output whose frequency Fvco is proportional to the input control voltage. 1/N divider 17 is a device that produces output signal Dout whose frequency is an integer (denoted by N) division of that of an input signal (output signal X of the PLL). When the frequency of the signal X is Fvco, the frequency of the signal Dout becomes Fvco/N. The signal Dout is input as the signal FB to the phase comparator 11.
2-to-1 multiplexer (MUX) 15 makes it possible to by-pass the PLL with a clock signal at input A. S is the control input for the multiplexer 15. The PLL can be by-passed by setting input S to 0 and clocking through input A. A zero-pulse (pulse width given in specification) on S resets the PLL to a hold state.
The above description of PLL functions suggests that PLL testing may be achieved by exercising the PLL under test (PUT) as follows.
Checking the xe2x80x9cstartxe2x80x9d sequence: This is the verification that the PLL could be brought up to frequency within a specified time from the time the system is started. This includes the verification of phase locking.
Normal mode operation: After phase lock, checks must be done to ascertain that the output signal of the PLL is at the desired frequency.
Changing frequency dynamically: This is the verification of the fact that the PLL could operate in various modes, such as system test mode, normal operation mode, etc. This may involve the reprogramming of the PLL in order to effect frequency change dynamically.
Checking the xe2x80x9cstopxe2x80x9d sequence: This is the verification that all chips being driven would stop at the stop of the PLL. This, together with the xe2x80x9cstartxe2x80x9d sequence check, verifies that the driven chips would cease and resume operation in tandem.
However, the PLL, like other high-frequency analog and mixed signal circuits, is difficult to test. Although most specification-based test schemes for the PLL perform the xe2x80x9cstartxe2x80x9d sequence checks and normal mode operation verification, dynamic change of frequency and xe2x80x9cstopxe2x80x9d sequence checks are not facilitated for.
Dalmia et al. have presented an operating current-monitoring method of PLL testing (M. Dalmia, A. Ivanov and S. Tabatabaei, xe2x80x9cPower Supply Current Monitoring Techniques for Testing PLLs,xe2x80x9d Proc. Sixth IEEE Asian Test Symposium, pp. 366-371, November 1997). The approach used in this method is not ad-hoc, however, currently it is difficult to implement a test scheme based on operating current measurement. Kim et al. have presented a defect-oriented method that realizes testing by taking the PLL operation through two dynamic transitions (S. Kim, M. Soma and D. Risbud, xe2x80x9cAn Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops, xe2x80x9dProc. 18th IEEE VLSI Test Symposium, April 2000). The method then measures the three stable frequencies for comparisons with the expected frequencies. However, their method does not perform the xe2x80x9cstartxe2x80x9d sequence check and it requires the addition of a significant amount of extra hardware.
It is an object of the present invention to provide a device for modified PLL testing which includes verification of dynamic change of frequency and/or a xe2x80x9cstartxe2x80x9d sequence check, and a method thereof.
The testing device according to the present invention comprises a reset circuit, an input circuit, an output circuit and a connection control circuit.
The reset circuit resets the phase-locked loop by disconnecting the charge pump from the loop filter and providing an alternative discharge path for the loop filter. The input circuit receives a feedback signal from an output of the phase-locked loop and a control signal, produces a combination signal from the received signals and inputs the combination signal to the phase-locked loop. The combination signal, together with a reference signal, causes the phase-locked loop to perform one of charging up the loop filter, discharging the loop filter and a normal operation. The output circuit outputs a signal with a frequency corresponding to an output of the voltage-controlled oscillator in cases that the phase-locked loop charges up the loop filter, that the phase-locked loop discharges the loop filter and that the phase-locked loop performs the normal operation. The connection control circuit controls connection between a digital circuit and an analog circuit of the phase-locked loop.